1. Technical Field of the Invention
The present invention relates to a power source circuit, in particular, a power source circuit, which can reduce power consumption and respond to load fluctuations at high speeds among power source integrated circuits of synchronous rectification systems using a complementary metal oxide semiconductor (CMOS) integrated circuit.
2. Description of the Related Art
Recently, mobile devices such as cellular phones have become widely used and the opportunities for driving a circuit being a load with a battery have been increasing such that it is essential that the power consumption of a power source circuit be small. Further, it is also essential that a power source circuit can respond to load fluctuations at high speeds.
In particular, the stabilized D.C. power source having a low voltage and low power consumption is required along with popularization of electronic equipment using integrated circuits.
If a power source is stabilized by a switch action of turning transistors “on” and “off” in response to fluctuations in the load and/or input, power consumed wastefully can be reduced such that the efficiency of the power is greatly improved. That is, changing the “on” period (or “on” duty) of the transistors can stabilize power source. As such, an efficient power source circuit, a synchronous rectification type switching regulator using a CMOS integrated circuit exists.
A CMOS integrated circuit is configured by using a combination of the two kinds of transistors of N-channel transistor (abbreviated to NMOS hereafter) and P-channel transistor (abbreviated to PMOS hereafter), and is the mainstream of the large scale integration (LSI) technique due to its low power consumption characteristic.
The configuration of a synchronous rectification type switching regulator using CMOS integrated circuit is shown in FIG. 14.
In FIG. 14, the power source circuit includes a synchronous rectification type CMOS inversion circuit including a PMOS (QP1) which is a high side transistor and a NMOS (QN1) which is a low side transistor and turning “on” or “off” the transistors alternately to output a D.C. voltage VOUT; an error amplifier 63 obtaining an error signal by comparing the output voltage from the CMOS inversion circuit with the reference voltage value of a reference voltage supply E; and an PWM circuit 61 controlling the output from the CMOS inversion circuit to be constant by controlling the pulse width of a Pulse Width Modulation signal based on the error signal.
The PWM circuit 61 outputs high frequency wave (for example, 1 MHz) pulses SH and SL which are approximately synchronized with each other and have appropriate pulse widths to apply the pulses to each gate of the PMOS (QP1) and the NMOS (QN1). The high frequency wave pulses SH and SL are such pulses as shown in FIG. 15(a) and (b) respectively. The transistors, the PMOS (QP1) and the NMOS (QN1), are connected in series as these drains D being in common between a terminal 24 to which a D.C. voltage VIN (equal to power source voltage VDD, for example, 4V) is supplied as a input voltage and a terminal 25 supplying a reference potential VSS (for example, 0.3V), and each transistor is turned “on” and “off” alternately by the high frequency wave pulses SH and SL which are approximately synchronized, thereby producing an A.C. voltage VMA as shown in FIG. 15(c) at the intermediate node K, which is the connection point. When the NMOS (QN1) is turned “on” during the “off” period of the PMOS (QP1), the intermediate node potential VMA once undershoot to a potential lower than the reference potential VSS and then returns from the undershot state to intersect with the VSS level at point P. The intermediate node potential VMA thereafter rises over the VSS level.
Here, the reason why the gate pulse SL supplied to the gate of the NMOS (QN1) is slightly delayed against the gate pulse SH of the PMOS (QP1) in FIG. 15(a), (b) is that the NMOS (QN1) is turned “on” after the PMOS (QP1) is certainly turned “off”, thereby preventing a through current from flowing from a power source VIN side to a reference potential VSS side by turning the PMOS and the NMOS “on” at the same time. In addition, a Schottky diode SD is connected between a source and a drain of the NMOS (QN1), thereby implementing an overvoltage protection of the NMOS and power supply backup when the NMOS is “off”.
A coil for rectification L1 and a stabilized capacitance C0 are connected in series between the intermediate node K and a terminal 26 giving the reference potential VSS so as to output a D.C. voltage VOUT smoothed by the stabilized capacitance C0 to an output terminal 27 connected to the series connection point. Further, the output voltage VOUT is fed back to one terminal of the error amplifier 63 via a feedback line so as to be compared with the reference voltage value at the reference voltage supply E connected to a terminal 28 giving the reference potential VSS. The error output, which is the result of the comparison by the error amplifier 63, is supplied to the PWM circuit 61 to control the pulse width of the PWM signal that the PWM circuit 61 produces by the error output. The output voltage VOUT (for example, 1.5V) supplied to a load not shown in the drawing is controlled to be constant all the time by this feedback control.
On the other hand, when a load of the regulator output VOUT rapidly changes, the PWM of a switching regulator must be also controlled in accordance with a load. Generally, when the feedback is from the output voltage VOUT responsiveness is low. Hence, the responsiveness to a load is improved by controlling in response to the change of the load current. Generally, the change in the current is monitored by providing a resistor or the like with an external regulator output stage.
For example, as shown in FIG. 16, a resistor for current detection RS is provided between the coil L1 and the output terminal 27 to amplify the potential difference across the resistor RS by an amplifier 62 and feed back to one terminal of the error amplifier 63. Or, the resistor for current detection RS is provided between the source S of the PMOS (QN1) and the terminal 24 to which the D.C. voltage VIN is input to feed back the potential difference across the resistor RS.
Meanwhile, in the power source circuit shown in FIG. 14, the waveform of the voltage VMA at the intermediate node K between the PMOS (QP1) and the NMOS (QN1) during operation is in the manner shown in FIG. 15(c). The NMOS (QN1) is turned “on” during the “off” period of the PMOS (QP1), thereby supplying power from the NMOS side to a load. Whereat, the potential of the intermediate node voltage VMA becomes lower than the reference potential VSS such that current flows from the reference potential VSS side to the intermediate node K side (namely, a load side).
However, when current consumption is small, namely, a load is light, there is a problem that the intermediate node potential VMA returns from the undershooting state to rise over the reference potential VSS during the “off” period of the NMOS (QN1) and current flows from the intermediate node K to the VSS side (namely, current flowing backward) such that power is consumed. Hence, controlling the NMOS (QN1) to be turned “off” is required.
On the other hand, though responsiveness to a load is improved by PWM control in response to the change of the load current, if the current change is monitored by providing a resistor or the like with an external regulator output stage, such providing a resistor causes problems that the component parts of the resistor causes a large increase in the number of component parts and the efficiency decrease due to loss at the resistor.
Therefore, an advantage of the present invention is to provide a power source circuit that can reduce power consumption and respond to load fluctuations at high speeds without an increase in the number of component parts and decreased efficiency in a power source circuit of a synchronous rectification system.